module counter(out, clk, reset);
	
	parameter WIDTH = 8;

	output [WIDTH - 1 : 0] out;
	input clk, reset;

	reg [WIDTH - 1 : 0] out;	// use reg for always
	wire clk, reset;

	always @(posedge clk)
		out <= out + 1;

	always @reset
		if (reset)
			assign out = 0;		// use assign in here???
		else
			deassign out;

endmodule